完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.contributor.author | Hsu, Che-Lun | en_US |
dc.contributor.author | Chen, Wen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:38:52Z | - |
dc.date.available | 2014-12-08T15:38:52Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-5309-2 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26621 | - |
dc.description.abstract | With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-mu m 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time. | en_US |
dc.language.iso | en_US | en_US |
dc.title | ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | en_US |
dc.citation.spage | 989 | en_US |
dc.citation.epage | 992 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000287216001058 | - |
顯示於類別: | 會議論文 |