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dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorHsu, Che-Lunen_US
dc.contributor.authorChen, Wen-Yien_US
dc.date.accessioned2014-12-08T15:38:52Z-
dc.date.available2014-12-08T15:38:52Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5309-2en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/26621-
dc.description.abstractWith high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-mu m 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.en_US
dc.language.isoen_USen_US
dc.titleESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchupen_US
dc.typeArticleen_US
dc.identifier.journal2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage989en_US
dc.citation.epage992en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000287216001058-
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