標題: ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup
作者: Ker, Ming-Dou
Hsu, Che-Lun
Chen, Wen-Yi
電機學院
College of Electrical and Computer Engineering
公開日期: 2010
摘要: With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-mu m 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.
URI: http://hdl.handle.net/11536/26621
ISBN: 978-1-4244-5309-2
ISSN: 0271-4302
期刊: 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
起始頁: 989
結束頁: 992
顯示於類別:會議論文