The effect of thermal treatment on device characteristic and reliability for sub-100-nm CMOSFETs

doi:10.1109/TDMR.2004.826590

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Yeh, WK	en_US
dc.contributor.author	Fang, YK	en_US
dc.contributor.author	Chen, MC	en_US
dc.date.accessioned	2014-12-08T15:39:08Z	-
dc.date.available	2014-12-08T15:39:08Z	-
dc.date.issued	2004-06-01	en_US
dc.identifier.issn	1530-4388	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TDMR.2004.826590	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26745	-
dc.description.abstract	The effect of post-thermal annealing after halo implantation on device characteristic and reliability of sub-100-nm CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced degradation. The best result of device performance and reliability was obtained by a post-thermal annealing treatment performed at medium temperatures (e.g., 900 degreesC) for a longer time (>1 min).	en_US
dc.language.iso	en_US	en_US
dc.subject	halo	en_US
dc.subject	hot-carrier-induced degradation	en_US
dc.subject	indium	en_US
dc.subject	post-thermal annealing	en_US
dc.title	The effect of thermal treatment on device characteristic and reliability for sub-100-nm CMOSFETs	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TDMR.2004.826590	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY	en_US
dc.citation.volume	4	en_US
dc.citation.issue	2	en_US
dc.citation.spage	256	en_US
dc.citation.epage	262	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000223030400016	-
dc.citation.woscount	1	-
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