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dc.contributor.authorChang, TCen_US
dc.contributor.authorYan, STen_US
dc.contributor.authorLiu, PTen_US
dc.contributor.authorChen, CWen_US
dc.contributor.authorWu, HHen_US
dc.contributor.authorSze, SMen_US
dc.date.accessioned2014-12-08T15:39:12Z-
dc.date.available2014-12-08T15:39:12Z-
dc.date.issued2004-05-03en_US
dc.identifier.issn0003-6951en_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.1739514en_US
dc.identifier.urihttp://hdl.handle.net/11536/26788-
dc.description.abstractThe leakage behavior of the quasi-superlattice structure has been characterized by current-voltage measurements at room temperature and 50 K. A resonant tunnelinglike leakage characteristic is observed at low temperature. The resonant tunneling occurs at around 2, 5.2, and 7 V under a gate voltage swept from 0 to 10 V. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-lattice structure and suggests that the considerations of the operating voltage for the two-bit per cell nonvolatile-memory device need to be taken into account. (C) 2004 American Institute of Physics.en_US
dc.language.isoen_USen_US
dc.titleLeakage behavior of the quasi-superlattice stack for multilevel charge storageen_US
dc.typeArticleen_US
dc.identifier.doi10.1063/1.1739514en_US
dc.identifier.journalAPPLIED PHYSICS LETTERSen_US
dc.citation.volume84en_US
dc.citation.issue18en_US
dc.citation.spage3687en_US
dc.citation.epage3689en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000221062500085-
dc.citation.woscount0-
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