完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Ta-Chuan | en_US |
dc.contributor.author | Wu, Chun-Yu | en_US |
dc.contributor.author | Chen, Sheng-Kai | en_US |
dc.contributor.author | Yu, Ming H. | en_US |
dc.contributor.author | Kang, Tsung-Kuei | en_US |
dc.contributor.author | Cheng, Huang-Chung | en_US |
dc.date.accessioned | 2014-12-08T15:39:18Z | - |
dc.date.available | 2014-12-08T15:39:18Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-7419-6 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26854 | - |
dc.description.abstract | For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000287997300213 | - |
顯示於類別: | 會議論文 |