標題: A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
作者: Liao, Ta-Chuan
Wu, Chun-Yu
Chen, Sheng-Kai
Yu, Ming H.
Kang, Tsung-Kuei
Cheng, Huang-Chung
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2010
摘要: For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
URI: http://hdl.handle.net/11536/26854
ISBN: 978-1-4244-7419-6
期刊: 2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST
顯示於類別:會議論文