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dc.contributor.authorLiao, Ta-Chuanen_US
dc.contributor.authorWu, Chun-Yuen_US
dc.contributor.authorChen, Sheng-Kaien_US
dc.contributor.authorYu, Ming H.en_US
dc.contributor.authorKang, Tsung-Kueien_US
dc.contributor.authorCheng, Huang-Chungen_US
dc.date.accessioned2014-12-08T15:39:18Z-
dc.date.available2014-12-08T15:39:18Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-7419-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/26854-
dc.description.abstractFor the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.en_US
dc.language.isoen_USen_US
dc.titleA New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applicationsen_US
dc.typeArticleen_US
dc.identifier.journal2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGESTen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287997300213-
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