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dc.contributor.authorLin, JCen_US
dc.contributor.authorYeh, WKen_US
dc.contributor.authorLei, TFen_US
dc.date.accessioned2014-12-08T15:39:26Z-
dc.date.available2014-12-08T15:39:26Z-
dc.date.issued2004-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.43.1737en_US
dc.identifier.urihttp://hdl.handle.net/11536/26921-
dc.description.abstractThe effect of post-thermal annealing (PA) after In-halo and As-halo implantation on the reliability of sub-0.1 mum complementary metal-oxide-semiconductor field-effect-transistors was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced device's degradation. The optimal results of device performance as well as of reliability can be obtained with post-annealing treatment performed at medium temperatures (e.g.. 900degreesC) for a longer time.en_US
dc.language.isoen_USen_US
dc.subjecthaloen_US
dc.subjectindiumen_US
dc.subjectpost-thermal annealingen_US
dc.subjecthot-carrier-induced device degradationen_US
dc.titleEfficient improvement of hot-carrier-induced device's degradation for sub-0.1 mu m complementary metal-oxide-semiconductor field-effect-transistor technologyen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1143/JJAP.43.1737en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume43en_US
dc.citation.issue4Ben_US
dc.citation.spage1737en_US
dc.citation.epage1741en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000221510800016-
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