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dc.contributor.authorWen, Yong-Ruen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorChen, Wen-Yien_US
dc.date.accessioned2014-12-08T15:39:26Z-
dc.date.available2014-12-08T15:39:26Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5431-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/26931-
dc.identifier.urihttp://dx.doi.org/10.1109/IRPS.2010.5488718en_US
dc.description.abstractBallast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.en_US
dc.language.isoen_USen_US
dc.titleA BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGYen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/IRPS.2010.5488718en_US
dc.identifier.journal2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUMen_US
dc.citation.spage857en_US
dc.citation.epage860en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287515600142-
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