標題: | Integration of a stack of two fluorine doped silicon oxide film with ULSI interconnect metallization |
作者: | Cheng, YL Wang, YL Liu, CP Wu, YL Lo, KY Liu, CW Lan, JK Ay, C Feng, MS 材料科學與工程學系 Department of Materials Science and Engineering |
關鍵字: | high density plasma (HDP);fluorosilicate glass (FSG);gap fill;capacitance;via resistance (Rc_Via);plasma-enhanced chemical vapor deposition (PECVD) |
公開日期: | 15-Jan-2004 |
摘要: | Recently, fluorosilicate glass (FSG) has received much attention for application in microelectronics manufacturing due to its low dielectric constant and stable gap-filling ability. Although FSG films have been demonstrated as potential inter metal dielectrics (IMD) for sub-micron devices, integrating a stack of two fluorine doped silicon oxide film deposited on a high-density plasma chemical vapor deposition (HDP-CVD) system for gap filling and a plasma-enhanced chemical vapor deposition (PECVD) system for throughput has not been fully investigated. In this research, an excellent and exceptionally stable process was demonstrated for a stack of HDP-CVD FSG and PECVD FSG layers. Cracks that result from multi-level metal technology were eliminated when higher compressive stress PECVD FSG film was implemented as a capping layer. An 11% capacitance reduction was achieved when comparing a stack of FSG films to undoped silicon oxide. No problem occurred for photo, via etching and chemical mechanical polishing of FSG film. The FSG layer stack's via resistance (Rc(-)Via) as well as a full HDP-FSG scheme is comparable. These results are very promising for the integration of FSG films as inter metal dielectric for devices. (C) 2003 Elsevier B.V. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.matchemphys.2003.08.023 http://hdl.handle.net/11536/27135 |
ISSN: | 0254-0584 |
DOI: | 10.1016/j.matchemphys.2003.08.023 |
期刊: | MATERIALS CHEMISTRY AND PHYSICS |
Volume: | 83 |
Issue: | 1 |
起始頁: | 150 |
結束頁: | 157 |
Appears in Collections: | Articles |
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