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dc.contributor.authorKer, MDen_US
dc.contributor.authorHsu, KCen_US
dc.date.accessioned2014-12-08T15:40:31Z-
dc.date.available2014-12-08T15:40:31Z-
dc.date.issued2003-08-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2003.814434en_US
dc.identifier.urihttp://hdl.handle.net/11536/27662-
dc.description.abstractThe turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V-SS and pad-to-V-DD ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-mum salicided CMOS process with the human body model (machine model) ESD level of similar to7.25 kV (500 V) in a small layout area.en_US
dc.language.isoen_USen_US
dc.subjectcomplementaryen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectESD protection circuiten_US
dc.subjectsilicon-controlled rectifier (SCR)en_US
dc.subjectsubstrate-triggered techniqueen_US
dc.titleLatchup-free ESD protection design with complementary substrate-triggered SCR devicesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2003.814434en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume38en_US
dc.citation.issue8en_US
dc.citation.spage1380en_US
dc.citation.epage1392en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000184371400009-
dc.citation.woscount24-
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