A High-Troughput Radix-4 Log-MAP Decoder With Low Complexity LLR Architecture

doi:10.1109/VDAT.2009.5158137

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DC 欄位	值	語言
dc.contributor.author	Chuang, Hsiang-Tsung	en_US
dc.contributor.author	Tseng, Kai-Hsin	en_US
dc.contributor.author	Fang, Wai-Chi	en_US
dc.date.accessioned	2014-12-08T15:41:09Z	-
dc.date.available	2014-12-08T15:41:09Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-2781-9	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28009	-
dc.identifier.uri	http://dx.doi.org/10.1109/VDAT.2009.5158137	en_US
dc.description.abstract	The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm(2) on UMC 0.13 mu m standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.	en_US
dc.language.iso	en_US	en_US
dc.title	A High-Troughput Radix-4 Log-MAP Decoder With Low Complexity LLR Architecture	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/VDAT.2009.5158137	en_US
dc.identifier.journal	2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM	en_US
dc.citation.spage	231	en_US
dc.citation.epage	234	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000271941200058	-
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