適用於802.11n之Radix-4 LDPC解碼器

Abstract

在本論文中，我們提出一種名為Radix-4的低密度同位檢查碼的解碼演算法，比較起傳統的解碼方式，可以得到更好誤碼率表現及吞吐量的增加。再者，我們將其實現在802.11n規格下分別為(1944,972)、(1296,648)及(648,324)，完成一顆支援3個模式的低密度同位檢查碼解碼器。我們採用部分平行的架構來減少晶片面積。在台積電18um的製程下，所提的解碼器可以在操作頻率62.5MHz達到292~50Mbps的吞吐量。其面積為17.9mm2 ，而在供應電壓為1.62V下，平均消耗功率為145mW。

In this thesis, a new decoding algorithm called Radix-4 LDPC decoder is used to increase the throughput and achieve better BER performance. Moreover, a three-size (1944,972), (1296,648), and (648,324) LDPC decoder applied to IEEE 802.11n standard is implemented. The partially parallel scheme is used to decrease chip area as well as routing resource. The LDPC decoder was implemented with TSMC CMOS 18um process. The proposed decoder can achieve 292∼50Mbps decoding throughput rate under clock frequency of 62.5MHz. The core size is 17.9 mm2 and average power consumption with a 1.62V voltage supply is 145mW.