適用於3GPP之Radix-4渦輪碼解碼器

Abstract

渦輪碼已經廣範使用在通訊系統，因為它有極佳的錯誤修正能力。為了增加扇出數和減少所需的記憶，開始研究渦輪碼radix-4架構。可是在radix-4的渦輪解碼器所需的計算路徑較長，使得radix-4渦輪解碼器的扇出數無法高於radix-2渦輪解碼器2倍。在這篇論文中我們在遞迴架構中提出一個查表方針，使得扇出數增加62%，在提出的方法下效能僅比Log-MAP差0.025dB。應用在超大型積體電路上，我們在輸入緩衝器使用dual-RAM取代成single-RAM，這樣可以減少面積57.8%及減少功率71.83%。晶片是採用TSMC 0.18 CMOS製程，操作頻率在167MHz，電壓為1.62伏特。使用3GPP規格碼率為1/3，扇出數為22Mb/s下，消耗功率為135mW，而晶片的面積為2.65 包含200K的邏輯閘數。

Turbo code has been widely used in communication systems, because of its outstanding error correction performance. To increase throughput and decrease the required memory. Radix-4 architecture for Turbo decoder was studied. However, the critical path of the recursive architecture in Radix-4 turbo decoder is long, As a result conventional Radix-4 architecture [15] cannot achieve twice throughput over the conventional Radix-2 architecture. In this thesis, we proposed a Look-Up Table scheme for the recursive architecture and the throughput increases up to 62%. The performance of the proposed scheme is worse than the Log-MAP (optimal) by only 0.025dB. In VLSI implementation, we propose a method for input buffer and it can reduce the dual-RAM by the single-RAM to save area and power. The proposed method can reduce the area by 57.8% and the power by 71.83%. The chip is fabricated in TSMC 0.18 μm CMOS process, operating at 167MHz clock rate with voltage supply 1.62V. The power consumption is 135mW at decoding rate 22Mb/s, with code rate 1/3 for 3GPP standard. The core area is 2.65 mm², contain 200K gate counts.