Turbo Code應用於3GPP硬體實現之研究

Abstract

Turbo Code 提供優越的錯誤更正能力，所以被廣泛應用在無線通訊方面的應用。然而由於其龐大的運算量，大量的記憶體消耗，及複雜的運算程序，造成硬體實作上無法容易實現。基於此，本論文將討論設計Turbo Code解碼器時一些重要的設計考量，並以3GPP的Turbo Code解碼器規格，為我們實現的對象。我們將以定點方式及可移動視窗方演算法實現3GPP規格Turbo Code解碼器，並分析其對系統效能的影響。我們所提出的架構，與之前提出相關的設計做比較，將大幅減少Turbo Code解碼器的複雜度。特別在記憶體方面，大約可以解省10%~17%的儲存位元。我們提出一個低成本的3GPP規格的Turbo Code解碼器之架構，並以VLSI方式實現成晶片。最後，我們以TSMC 0.35um 1P4M COMS的製程製造這顆晶片，其操作頻率最高達50M Hz，並符合3GPP之重要規格。

Turbo Coding offers excellent capabilities of error correction and thus has been getting popular in the state-of-the-art wireless applications. However, the implementation of turbo coding requires high computing power and large memory size. How to optimize the use of computing resources and memory requirement becomes a key to design turbo coding VLSI. The thesis, therefore, addresses the critical implementation issues in terms of processing elements and memory, targeting on the turbo coding for 3GPP. Using the sliding-window algorithm, the proposed turbo coding architecture significantly reduces the implementation cost while the performance results satisfy the 3GPP specifications. Following the cell-based design flow, the thesis realizes a turbo decoder chip using TSMC 0.35mm 1P4M CMOS processes with 50MHz operation frequency. Comparing with the other reported turbo decoders, the chip saves the memory size by 10%~17% and consumes low power.