A design-for-verification technique for functional pattern reduction

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liu, CNJ	en_US
dc.contributor.author	Chen, IL	en_US
dc.contributor.author	Jou, JY	en_US
dc.date.accessioned	2014-12-08T15:41:17Z	-
dc.date.available	2014-12-08T15:41:17Z	-
dc.date.issued	2003-03-01	en_US
dc.identifier.issn	0740-7475	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/MDT.2003.1188262	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28080	-
dc.description.abstract	This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.	en_US
dc.language.iso	en_US	en_US
dc.title	A design-for-verification technique for functional pattern reduction	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/MDT.2003.1188262	en_US
dc.identifier.journal	IEEE DESIGN & TEST OF COMPUTERS	en_US
dc.citation.volume	20	en_US
dc.citation.issue	2	en_US
dc.citation.spage	48	en_US
dc.citation.epage	55	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000181420400012	-
dc.citation.woscount	4	-
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