標題: | Reduce the memory bandwidth of 3D graphics hardware with a novel rasterizer |
作者: | Chen, CH Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | graphics processor;rasterizer;hierarchical Z-buffer |
公開日期: | 1-Aug-2002 |
摘要: | Currently, memory bandwidth has become the main bottleneck in graphics system. Reducing the memory access can reduce the power consumption and boost overall system performance. Low power technique is more important for graphics applications on hand-held or mobile device. In this paper, we propose a novel visibility driven rasterizer to reduce the memory access and operations on invisible pixels. It integrates with two-level hierarchical Z-buffer to do visibility driven rasterization. The rasterization scheme is tile-order scan-line based, and the rasterizer can smartly change the tile-size depending on the triangle size. This technique can balance the rasterization loading under different triangles. Moreover, we propose a fast visibility test algorithm to quickly reject a group of pixels within the tile. Simulation results show that the overall bandwidth reduction can be up to 60% under our test images. |
URI: | http://dx.doi.org/10.1142/S0218126602000525 http://hdl.handle.net/11536/28630 |
ISSN: | 0218-1266 |
DOI: | 10.1142/S0218126602000525 |
期刊: | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Volume: | 11 |
Issue: | 4 |
起始頁: | 377 |
結束頁: | 391 |
Appears in Collections: | Articles |
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