Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses

Abstract

Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-mu m CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.