標題: Cycle time estimation for wafer fab with engineering lots
作者: Chung, SH
Huang, HW
工業工程與管理學系
Department of Industrial Engineering and Management
公開日期: 1-Feb-2002
摘要: Due to the interaction between the process complexity and equipment diversity in a wafer fab, it is rather difficult to estimate the material flow time of wafer lots. Facing competition, it is common for a wafer fab to produce a certain quantity of engineering lots. However, introducing engineering lots into the factory will increase the complexity of the material flow control and the difficulty in cycle time estimation. The purpose of this paper is to develop cycle time estimation algorithms for a wafer fab by analyzing the material flow characteristics. Simulation results have shown that the algorithm is capable of generating satisfactory cycle time estimations with or without existing engineering lots.
URI: http://dx.doi.org/10.1023/A:1011935728647
http://hdl.handle.net/11536/29030
ISSN: 0740-817X
DOI: 10.1023/A:1011935728647
期刊: IIE TRANSACTIONS
Volume: 34
Issue: 2
起始頁: 105
結束頁: 118
Appears in Collections:Articles


Files in This Item:

  1. 000171291800002.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.