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dc.contributor.authorTsui, BYen_US
dc.contributor.authorYang, TJen_US
dc.contributor.authorKu, TKen_US
dc.date.accessioned2014-12-08T15:43:19Z-
dc.date.available2014-12-08T15:43:19Z-
dc.date.issued2001-11-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0026-2714(01)00090-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/29316-
dc.description.abstractSputter clean had been accepted as an effective surface clean process prior to metal deposition. In this work, the impact of interface nature on via resistance of Al-interconnect as via size is scaled down to 0.16 mum was studied. Al-F compound was identified as the main interfacial contaminants after standard post-etch clean process if the TiN laver of the underlying metal line were etched through during via etch. For via size larger than 0.25 mum (aspect ratio lower than 3.2), Al-F compound can be removed by sputter clean effectively. However, below 0.25 mum, sputter clean efficiency decreases such that via resistance is degraded by the existence of Al-F interfacial layer. On the other hand, sputter clean results in oxide re-deposition, which in turn degrades via resistance. It is suggested that to obtain low resistance sub-0.2 mum via, via etch must stop on TiN layer such that no Al-F layer can be formed. Otherwise, new interfacial layer clean technology with high efficiency and without side effect has to be developed. (C) 2001 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleImpact of interface nature on deep sub-micron Al-plug resistanceen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/S0026-2714(01)00090-7en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume41en_US
dc.citation.issue11en_US
dc.citation.spage1889en_US
dc.citation.epage1896en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000172356800018-
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