標題: A method to characterize n(+)-polysilicon/oxide interface traps in ultrathin oxides
作者: Chang, KM
Chung, YH
Lee, TC
Sun, YL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-六月-2001
摘要: In this study, a new method to characterize the n(+)-polysilicon/oxide interface trap state by measuring the gate voltage-gate leakage current (Vg-Jg) characteristics under the low electric field is developed. These traps are neutral and consist of the fast and slow trap states located near the Fermi level of the n(+)-polyoxide. We use the first order rate equation to characterize the relationship between the gate leakage current and the gate voltage sweep rate. A simple formula to characterize the detrapping behavior of the slow trap states with the detrapping time constant was derived. It is important to find that the smaller detrapping time constant observed in a thinner oxide (2.5 nm) is due to the field enhanced detrapping effect. (C) 2001 The Electrochemical Society.
URI: http://dx.doi.org/10.1149/1.1370416
http://hdl.handle.net/11536/29625
ISSN: 1099-0062
DOI: 10.1149/1.1370416
期刊: ELECTROCHEMICAL AND SOLID STATE LETTERS
Volume: 4
Issue: 6
起始頁: G47
結束頁: G49
顯示於類別:期刊論文