標題: Fault coverage and defect level estimation models for partially testable MCMs
作者: Tseng, WD
Wang, K
資訊工程學系
Department of Computer Science
公開日期: 1-四月-2000
摘要: The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault covet-age, lest methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model.
URI: http://dx.doi.org/10.1049/ip-cds:19990198
http://hdl.handle.net/11536/30622
ISSN: 1350-2409
DOI: 10.1049/ip-cds:19990198
期刊: IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS
Volume: 147
Issue: 2
起始頁: 119
結束頁: 124
顯示於類別:期刊論文


文件中的檔案:

  1. 000087175900004.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。