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dc.contributor.authorCheng, HCen_US
dc.contributor.authorHuang, CYen_US
dc.contributor.authorWang, FSen_US
dc.contributor.authorLin, KHen_US
dc.contributor.authorTarntair, FGen_US
dc.date.accessioned2014-12-08T15:45:47Z-
dc.date.available2014-12-08T15:45:47Z-
dc.date.issued2000-01-15en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.39.L19en_US
dc.identifier.urihttp://hdl.handle.net/11536/30804-
dc.description.abstractA novel two-step rapid thermal annealing (RTA) process has been developed to significantly reduce the crystallization time for the solid-phase crystallization (SPC) of amorphous silicon films. In comparison with the conventional SPC processes, it not only keeps a low thermal budget but also achieves a larger poly-Si film grain size than that obtained by one-step RTA, and even as large as that obtained by conventional furnace annealing (CFA). Furthermore, poly-Si thin-film transistors fabricated by such a novel annealing scheme possess electrical characteristics superior to those obtained by one-step RTA and comparable to those obtained by long-time CFA.en_US
dc.language.isoen_USen_US
dc.subjectSPCen_US
dc.subjectRTAen_US
dc.subjectCFAen_US
dc.subjectpoly-Si TFTsen_US
dc.subjecttwo-step RTAen_US
dc.titleThin-film transistors with polycrystalline silicon films prepared by two-step rapid thermal annealingen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.39.L19en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERSen_US
dc.citation.volume39en_US
dc.citation.issue1ABen_US
dc.citation.spageL19en_US
dc.citation.epageL21en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000085480000006-
dc.citation.woscount13-
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