標題: A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
作者: Chang, Ming-Hung
Chuang, Li-Pu
Chang, I-Ming
Hwang, Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2008
摘要: A 300mV 20MHz-35OMHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 mu W at 40MHz/300mV.
URI: http://hdl.handle.net/11536/30909
ISBN: 978-1-4244-2596-9
期刊: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
起始頁: 97
結束頁: 100
Appears in Collections:Conferences Paper