Title: | A compiled-code parallel pattern logic simulator with inertial delay model |
Authors: | Huang, KC Lee, CL Chen, JE 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | logic simulator;compiled code simulation;parallel pattern;inertial delay model;potential change frame |
Issue Date: | 1-Nov-1999 |
Abstract: | This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation. |
URI: | http://hdl.handle.net/11536/31022 |
ISSN: | 1016-2364 |
Journal: | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Volume: | 15 |
Issue: | 6 |
Begin Page: | 885 |
End Page: | 897 |
Appears in Collections: | Articles |
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