標題: Instruction set extension exploration in multiple-issue architecture
作者: Wu, I-Wei
Chen, Zhi-Yuan
Shann, Jyh-Jiun
Chung, Chung-Ping
資訊工程學系
Department of Computer Science
公開日期: 2008
摘要: To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement. This is because most algorithms overlook two important considerations: (1) only packing the operations lying on the critical path into ISE can improve performance; (2) the critical path usually changes after packing operations into an ISE. With these considerations, this paper presents an algorithm for ISE exploration based on list scheduling and Ant Colony Optimization (ACO), in which combines ISE exploration and the critical path identification (i.e. instruction scheduling). Results indicate that our approach outperforms the previous work in both performance improvement and area efficiency.
URI: http://hdl.handle.net/11536/31542
ISBN: 978-3-9810801-3-1
ISSN: 1530-1591
期刊: 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3
起始頁: 680
結束頁: 685
顯示於類別:會議論文