標題: Instruction set extension generation with considering physical constraints
作者: Wu, I-Wei
Huang, Shih-Chia
Chung, Chung-Ping
Shann, Jyh-Jiun
資訊工程學系
Department of Computer Science
關鍵字: instruction set extension;ASIP;extensible processors;pipestage timing constraint
公開日期: 2007
摘要: In this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.
URI: http://hdl.handle.net/11536/8346
ISBN: 978-3-540-69337-6
ISSN: 0302-9743
期刊: High Performance Embedded Architectures and Compilers, Proceedings
Volume: 4367
起始頁: 291
結束頁: 305
顯示於類別:會議論文