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dc.contributor.authorChen, Pei-Yuen_US
dc.contributor.authorVan, Lan-Daen_US
dc.contributor.authorReddy, Hari C.en_US
dc.contributor.authorLin, Chin-Tengen_US
dc.date.accessioned2014-12-08T15:47:27Z-
dc.date.available2014-12-08T15:47:27Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2341-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/31809-
dc.description.abstractIn this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.en_US
dc.language.isoen_USen_US
dc.titleA New VLSI 2-D Diagonal-Symmetry Filter Architecture Designen_US
dc.typeArticleen_US
dc.identifier.journal2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4en_US
dc.citation.spage320en_US
dc.citation.epage323en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000268007100079-
Appears in Collections:Conferences Paper