Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, Pei-Yu | en_US |
dc.contributor.author | Van, Lan-Da | en_US |
dc.contributor.author | Reddy, Hari C. | en_US |
dc.contributor.author | Lin, Chin-Teng | en_US |
dc.date.accessioned | 2014-12-08T15:47:27Z | - |
dc.date.available | 2014-12-08T15:47:27Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-4244-2341-5 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31809 | - |
dc.description.abstract | In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A New VLSI 2-D Diagonal-Symmetry Filter Architecture Design | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 | en_US |
dc.citation.spage | 320 | en_US |
dc.citation.epage | 323 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000268007100079 | - |
Appears in Collections: | Conferences Paper |