Cycle-Time-Aware Sequential Way-Access Set-Associative Cache for Low Energy Consumption

Abstract

In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.