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dc.contributor.authorHo, Y. H.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorChen, H. H.en_US
dc.date.accessioned2014-12-08T15:47:46Z-
dc.date.available2014-12-08T15:47:46Z-
dc.date.issued2010-11-01en_US
dc.identifier.issn0003-6951en_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.3508956en_US
dc.identifier.urihttp://hdl.handle.net/11536/31951-
dc.description.abstractThe charge loss mechanism of a two-bit wrapped-gate nitride storage nonvolatile memory is investigated. From retention measurements, it was shown that both vertical and lateral charge loss coexist. As a result of the misalignment of carriers, the lateral charge loss was caused by the hole accumulation near the junction and migrating toward the channel. By using a scaling of the word-gate length or a substrate-transient hot hole erase scheme, the charge loss in the lateral direction can be suppressed. Also, from the retention test, the latter scheme, substrate-transient hot hole (STHH), has a window independent of the word-gate length, which is better for the device scaling. (C) 2010 American Institute of Physics. [doi:10.1063/1.3508956]en_US
dc.language.isoen_USen_US
dc.titleThe investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memoryen_US
dc.typeArticleen_US
dc.identifier.doi10.1063/1.3508956en_US
dc.identifier.journalAPPLIED PHYSICS LETTERSen_US
dc.citation.volume97en_US
dc.citation.issue18en_US
dc.citation.spageen_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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