標題: Improving electrical performance of the scaled low-temperature poly-Si thin film transistors using vacuum encapsulation technique
作者: Lin, Wei-Kai
Liao, Ta-Chuan
Wu, Chun-Yu
Tu, Shih-Wei
Liu, Yen-Ting
Lin, Jun-Quan
Cheng, Huang-Chung
Chien, Feng-Tso
Chen, Wan-Lu
Chen, Chii-Wen
Tai, Ya-Hsiang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2008
摘要: A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain Junction..
URI: http://hdl.handle.net/11536/32686
ISSN: 0097-966X
期刊: 2008 SID INTERNATIONAL SYMPOSIUM, DIGEST OF TECHNICAL PAPERS, VOL XXXIX, BOOKS I-III
Volume: 39
起始頁: 1192
結束頁: 1195
Appears in Collections:Conferences Paper