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dc.contributor.authorCHEN, JEen_US
dc.contributor.authorLEE, CLen_US
dc.contributor.authorSHEN, WZen_US
dc.date.accessioned2014-12-08T15:05:05Z-
dc.date.available2014-12-08T15:05:05Z-
dc.date.issued1991-12-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/43.103505en_US
dc.identifier.urihttp://hdl.handle.net/11536/3618-
dc.description.abstractThis paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults. This procedure has been applied to collapse faults for 31 benchmark sequential circuits [1] and the number of faults has collapsed to 43% of the original number.en_US
dc.language.isoen_USen_US
dc.titleSINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITSen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/43.103505en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume10en_US
dc.citation.issue12en_US
dc.citation.spage1559en_US
dc.citation.epage1568en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1991GP77400009-
dc.citation.woscount7-
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