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dc.contributor.authorCHANG, MFen_US
dc.contributor.authorFUCHS, WKen_US
dc.date.accessioned2014-12-08T15:05:15Z-
dc.date.available2014-12-08T15:05:15Z-
dc.date.issued1991-05-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/4.78242en_US
dc.identifier.urihttp://hdl.handle.net/11536/3792-
dc.description.abstractDesign and reconfiguration approaches for high harvest rates and parallel on-wafer diagnosis of linear arrays are described in this paper. The defect-tolerant designs employ multiplexors to switch intercell connections and guarantee that the wire length between any two logically adjacent cells is constant, independent of fault distribution. The designs are appropriate for implementing linear arrays of wafer-scale memory and processor architectures. The harvesting of fault-free cells into a linear array is a percolation process; there exists a critical cell yield such that the harvest rate drops to zero (approaches 100%) if the cell yield is below (above) the critical value. Finding a maximum-size linear array for a given set of fault-free cells is polynomial time solvable if only the interconnections between fault-free cells are utilized, but is NP-complete if the interconnections between all cells are utilized. A heuristic reconfiguration algorithm utilizing the interconnections between all cells is presented. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is described.en_US
dc.language.isoen_USen_US
dc.titleLOOP-BASED DESIGN AND RECONFIGURATION OF WAFER-SCALE LINEAR ARRAYS WITH HIGH HARVEST RATESen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/4.78242en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume26en_US
dc.citation.issue5en_US
dc.citation.spage717en_US
dc.citation.epage726en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1991FG74400004-
dc.citation.woscount0-
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