高壓製程之靜電放電防護元件設計

Abstract

在高電壓(High-Voltage)靜電放電(Electrostatic Discharge, ESD)防護元件中[如：橫向擴散金氧半功率電晶體(LDMOS Power Transistor)、金氧半電晶體(MOSFET)、矽控整流器(SCR)、雙載子電晶體(BJT)、二極體(Diode)和場氧化電晶體(Field Oxide Device, FOD)]，BCD(Bipolar CMOS DMOS)製程技術中的橫向擴散金氧半功率電晶體由於其可以同時作為輸出級電流驅動(Output Current Driver)及靜電放電防護元件，故在應用面上相當廣泛，目前使用在薄膜液晶顯示器驅動器(LCD Driver)、電源管理積體電路 (Power Management IC)和汽車電子(Motor Electronics)等領域。而金氧半電晶體、矽控整流器、雙載子電晶體、二極體及場氧化電晶體則用作單純的靜電放電防護元件。矽控整流器是由電流驅動而導通的元件，在高壓靜電放電防護上由於其過高的觸發電壓(Trigger Voltage)和過低的持有電壓(Holding Voltage)，不是造成內部電路先損壞就是造成閂鎖效應(Latchup)發生，所以要加上額外的驅動電路或是透過調變佈局參數(Layout Parameter)去使觸發電壓降低和使持有電壓超過元件之工作電壓(Operation Voltage)，如此才可作為高壓靜電放電防護元件。 在本論文中首先會介紹各種已經被驗證的元件觸發方法去快速地將靜電放電能量排放及有效率地保護內部電路之氧化層，有使用當靜電放電發生時就處於導通狀況(Initial-on)的寄生(Parasitic)元件去觸發的靜電放電防護元件、原生性N型金氧半電晶體觸發矽控整流器(Native-NMOS-Triggered SCR, NANSCR)、外加的元件觸發電路、閘極耦合(Gate-Couple)、基體觸發(Substrate-Trigger)技術、假閘極(Dummy-Gate)結構去取代原本的隔離區(Isolation Region)之結構及透過佈局參數的改變達成元件自身基體觸發導通(Self-Substrate-Trigger)去增加元件觸發的速度。 另外會介紹智慧功率積體電路技術(Smart Power Integrated Circuit Technology)的應用領域及各種功率電晶體[包括：V型槽金氧半電晶體(VMOS)、U型槽金氧半電晶體(UMOS)、橫向擴散金氧半功率電晶體]在導通電阻(Turn-On Resistance)上和傳統金氧半電晶體有何差異使其可應用於輸出級電流驅動。接著介紹橫向擴散金氧半功率電晶體的元件導通機制(Turn-On Mechanism)和由於其特殊的元件結構造成之雙重驟回崩潰(Double-Snapback)機制。 本論文研究的第一部分是探討在0.25□m 18V BCD製程中各種佈局參數下的測試元件(Testkey)，其中包括高壓N型橫向擴散金氧半功率電晶體、高壓P型橫向擴散金氧半功率電晶體、高壓N型場氧化電晶體、高壓雙向矽控整流器及高壓N型矽控整流器(NSCR)。分別觀察其直流I-V特性及傳輸線觸波脈衝(Transmission Line Pulse) I-V特性，發現在高壓N型橫向擴散金氧半功率電晶體中在調變汲極端之N型擴散邊緣至電接觸的距離(N+ edge to contact spacing)由1□m至4□m時，由於其元件表面上的電阻值提升而使電流路徑由元件表面改變成元件深處，其二次崩潰電流(Secondary Breakdown Current, It2)由原本之0.4A上升至2.5A。在高壓P型橫向擴散金氧半功率電晶體方面則是發現P型金氧半電晶體的二次崩潰電流值在大幅調變元件的總寬度(Total Width)後只提昇了少許，在調變其他佈局參數並無法使其二次崩潰電流值能夠有效提升。在高壓N型場氧化電晶體及高壓N型矽控整流器則也可以透過調變汲極端之N型擴散邊緣至電接觸的距離去提升ESD耐受度。而在高壓雙向矽控整流器中則是發現雖然在傳輸線觸波產生系統的量測下持有電壓可透過調變參數去超過工作電壓，但是在直流I-V上所觀測到的卻是只有約2V。 本論文研究的第二部分則是介紹由製程(Process)方面去達到高壓靜電放電防護之能力。首先說明N型橫向擴散金氧半功率電晶體的詳細失效機制(Failure Mechanism)。在了解其失效機制後針對其失效點去做改善，目前已有方法有效地使寄生於N型橫向擴散金氧半功率電晶體的雙載子電晶體延緩進入導通狀態，其方法為分別在汲極端和源極端下方加入N型重摻雜和P型重摻雜，使汲極端N/N+接面要達成雪崩崩潰(Avalanche Breakdown)所需的觸發電流上升及使源極端之β gain下降造成雙載子電晶體所需觸發電壓上升。而在本BCD製程中提供了一道P型重摻雜的PSB(P type Sub Body)光罩於N型橫向擴散金氧半功率電晶體的源極和基體端下方，去比較在小型元件(Small Device)和大型元件(Large Device)上在加入此道光罩後對靜電放電防護有何影響。 在小型元件上加入此道光罩可使觸發電壓及持有電壓同時上升，但卻會有部份元件因為過大的持有電壓而使二次崩潰電流些微下降；在大型元件上加入此道光罩可使此元件不進入驟回崩潰狀態而將不均勻導通情況改善，同時將此元件可導通的電流達到了此元件能夠承受的最高值。

The high-voltage (HV) ESD (Electrostatic Discharge, ESD) protection devices including the LDMOS power transistor, MOSFET, SCR (Silicon Controlled Rectifier), BJT (Bipolar Junction Transistor), diode and FOD (Field Oxide Device). The LDMOS in BCD (Bipolar CMOS DMOS) process can be the output current driver and ESD protection device, simultaneously. Therefore, it is applied in the fields of LCD driver, power management IC and motor electronics, etc. The MOSFET, SCR, BJT, diode and FOD are for the ESD protection device only. The SCR is a current-triggered device and it suffers the high trigger voltage and low holding voltage issues in HV ESD protection. It is necessary to add the trigger circuit and modify the layout parameter to reduce the trigger voltage and increase the holding voltage to protect the internal circuits and avoid the latchup effect. The various trigger methods to reduce the trigger voltage will be introduced first. The methods are parasitic initial-on PMOS-triggered device, native-NMOS-triggered SCR, dual-direction SCR trigger circuit, gate-couple, substrate trigger, dummy-gate structure and self-substrate-trigger. In addition, the application fields and turn-on resistance of smart power integrated circuit technology will be also introduced to discuss the reason of the VMOS, UMOS and LDMOS can be the output current driver. Then, to investigate the turn-on mechanism and the double-snapback characteristic of the LD-NMOS. The first research of this thesis is to discuss the ESD performance of HV LD-NMOS, HV LD-PMOS, HV NFOD, HV dual-direction SCR and HV NSCR by layout modification in 0.25□m 18V BCD process. In TLP (Transmission Line Pulse) measurement, the ESD performance of LD-NMOS, NFOD and NSCR can be improved by increasing the N+ edge to contact spacing of the drain side due to the current path change. Unfortunately, the It2 (Secondary Breakdown Current) value can be improved a little by larger device total width of LD-PMOS. By layout modification, the holding voltage of dual-direction SCR can be controlled to over the operation voltage. But, the holding voltage of dual-direction SCR measured by 370A is different from the data measured by the TLP system is found. The second research of this thesis is to discuss the ESD performance of the small and large LD-NMOS devices with the PSB (P type Sub Body) layer. Due to the failure mechanism of the LD-NMOS is due to the snapback characteristic. The PSB layer is added to reduce the base resistance of the parasitic BJT and increase the trigger voltage of the LD-NMOS. Once the β gain decreased, the turn-on uniformity can be improved. The holding and trigger voltage can be both increased by the PSB layer in small LD-NMOS device; The It2 value can be increased by the PSB layer in large LD-NMOS device substantially.