Wimax應用之快速傅立葉轉換軟硬體共同設計

Abstract

簡單的說，如果一個處理器有處理1000 MIPS的能力，則它願意提供多少MIPS給快速傅立葉轉換運算，然後根據此MIPS去決定最適合此運算的N點分支傅立葉轉換硬體對於無線和行動通訊系統，傅立葉轉換模組是不可或缺的部分，特別是當寬頻無線系統需要一個高速且低功率硬體於高速封包式資料傳輸，這使得傅立葉轉換成為下一代無線系統必要的要求。在經過處理器運算量分析後，N點分支傅立葉轉換以硬體系統需要一個高速且低功率硬體於高速封包式資料傳輸，這使得傅立葉轉換成為下一代無線系統必要的需求。一般而言，傅立葉轉換模組的設計會針對特定的系統，因此，希望能去設計一個可以適合不同標準規格的傅立葉轉換模組。在此論文中採用處理器彈性的特色和硬體具有加速的機制去建立一個傅立葉轉換模組，並且可以符合IEEE 802.11n /16e的規格要求。除此之外，我們提出對於單輸入輸出/多輸實現於系統中，並且它已16位元及85MHz產出率(Throughput rate)為規格。之後，我們有針對是用於系統的傅立葉轉換架構做分析比較。最後，不只有對8點分支傅立葉轉換於FPGA上做驗證，並且有針對提出的排程做驗證是可以滿足IEEE 802.11n/16e的規格。

Briefly speaking, if a processor can process 1000 MIPS, it will provide which MIPS for us to operate Fast Fourier Transform (FFT). According to the MIPS it provides us, we can decide which N-points branch FFT of ASIC is suitable for us. FFT module is an indispensable part for wireless and mobile communication, especially when broadband wireless systems require a high speed and low power hardware module for its packet-based high-speed data transfer. This has made the design of FFT processor a critical requirement for the next generation wireless systems. In general, FFT module is designed for specific system. Therefore, it is desirable to design adaptive FFT module for different standards. This thesis adopts processor flexible characteristic and ASIC accelerated mechanism to set up a flexible FFT module which can meet IEEE 802.11n/16e standards. Besides, we propose optimized timing schedule for SISO/MIMO systems. After processor computational analysis, 64-points branch FFT of ASIC can be applied in proposed system and it computes 16-bits input data at a throughput rate of 85MHz. After that, we compare various pipeline-based FFT architectures suited to our system. Finally, it not only verifies the 8-points branch FFT on FPGA, but also checks proposed timing schedule which can satisfy IEEE 802.11n/16e specification.