标题: 新式复晶矽奈米线元件制作与特性分析
Fabrication and Characterization of Novel Poly-Si Nanowire Devices
作者: 刘大伟
Liu Ta Wei
林鸿志
黄调元
Horng-Chih Lin
Tiao-Yuan Huang
电子研究所
关键字: 表面体积比;环绕全闸极;电荷储存能力;忍耐力;记忆窗;surface-to-volume ratio;gate-all-around;retention;endurance;memory window
公开日期: 2007
摘要: 在本篇论文中,我们利用简单、低成本而且富变化性的方法制作数种具有相同奈米线型状,但是不同闸极组态的复晶矽奈米线元件,这些元件有助于我们探讨多闸极对于奈米线元件的基本电性和特性变异度的影响。相较于平面结构元件,实验结果证明奈米线具有较好的次临界摆幅(subthreshold swing)、较低的漏电流,以及较大的开关电流比(on/off current ratio)。我们实验的数据也显示,当奈米线的通道表面被闸极覆盖的比例愈大时,由于具有较高的表面体积比(surface-to-volume ratio),会展现出更好的特性。我们也藉由临界电压(threshold voltage)的标准差和闸极宽度、长度乘积开根号( )的关系来探讨不同元件之间特性的变异度,发现环绕全闸极(gate-all-around)结构的奈米线元件呈现出最稳定的临界电压控制能力,而平面元件由于有较大的空乏区以及较差的电浆修补效果,因此不同元件之间的临界电压差异性较大。
此外,我们也制作三闸极(tri-gate)奈米线结构的SONOS元件。相较于平面结构,奈米线元件的写入和抹除速度有很明显的改善;在可靠度议题方面,奈米线元件拥有不错的电荷储存能力(retention)和忍耐力(endurance),它可以承受超过10000次的重复写入/抹除,并且在十年后仍然维持大于0.5V的记忆窗(memory window)。
In this thesis, several multiple-gated (MG) poly-Si nanowire (NW) devices were fabricated and characterized. Our fabrication process is simple, low cot, and flexible for fabricating devices with identical NW structure but different gate configuration. It thus allows us to investigate the impacts of MG on the basic electrical characteristics as well as the variation of devices. The experimental results show that, as compared with devices with planar structure, much improved device characteristics in terms of better subthreshold swing, lower leakage, and higher on/off ratio are obtained. Among all NW structures, superior device performance is achieved as the gated portion of NW channel surface increases, owing to the higher surface-to-volume ratio. We also study the device variation issue by plotting the standard deviation of VTH as a function of . We found that the device with gate-all-around configuration exhibits the best control in terms of the variation. Besides, the deviation of planar devices is evidently higher than the NW ones because of wider depletion width and worse plasma treatment efficiency.
Tri-gated SONOS devices were also fabricated and characterized with a process flow modified from the aforementioned one. It is confirmed that the NW devices have higher P/E speed than planar ones. For reliability issue, NW SONOS devices possess good retention and endurance characteristics. The memory window is larger than 0.5V after 10 years for a device after subjecting to 104 times of P/E cycles.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511507
http://hdl.handle.net/11536/38052
显示于类别:Thesis


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