複晶矽雙閘極薄膜電晶體特性及電性擾動分析

Abstract

在本篇論文中，我們製作了複晶矽雙閘極的平面結構電晶體並探討其特性。實驗發現縮小通道層的厚度，得到較好的閘極耦合效應，從而改善了次臨界擺幅 (subthreshold swing)和得到較高的開關電流比 (on/off current ratio)。另外，由於閘極的耦合效應，只要在控制閘極施加適當的固定偏壓，便可彈性地調整臨界電壓(threshold voltage)的大小。本論文也針對體反轉(volume inversion)的現象進行探索與分析。 除此之外，在本論文裡，我們也探討了一種複晶矽雙閘極奈米線電晶體的基本電性擾動分析。從我們實驗數據顯示，元件量測所得之臨界電壓的標準差與閘極寬度、長度乘積開根號成一個倒數的關係，與前人的模擬結果有同樣的趨向，我們也推測與複晶矽奈米線通道中的缺陷密度有一密切的關聯性。電漿處理可以有效的修補通道裡的缺陷，使元件之間的臨界電壓差異性降低。此外，在不同的操作模式下，以雙閘極操作模式，可得到最小的臨界電壓標準差。另外，我們的實驗數據也首次證實：當控制閘極的固定偏壓存在著一個最佳值，能有效地壓抑臨界電壓的差異性。

In this thesis, planar DG-TFTs were fabricated and characterized. With thin poly-Si body (30nm), gate-to-gate coupling effect in DG mode is more prominent, resulting in better gate controllability, higher ON-current and steeper sub-threshold swing (SS), compared with the single-gated mode. And, there is a significant enhancement in drain current under DG mode due to the volume inversion. In addition, threshold voltage can be modulated over a wide range by VTH-control gate (back gate). Compared with symmetric gate oxide, subthreshold swing can be slightly improved by using thicker Vth-control gate oxide to gain higher Ion/Ioff ratio. In this study, we also explore the threshold voltage variation in nanowire DG-TFTs. It is confirmed that threshold voltage fluctuation is inversely proportional to channel length and width. NH3-plasma treatment can effectively suppress threshold voltage fluctuation owing to the passivation of the trap states. It is also found that there is an optimum back gate bias for suppressing the short channel effect which may lead to a larger threshold voltage variation.