金屬矽化物-高介電常數介電質-半導體場效應電晶體之電性研究

Abstract

隨著超大型積體電路技術的不斷發展、元件尺寸的微縮，閘極介電質的厚度必須降低以維持電容值。但漏電流隨著厚度減少而不斷的增加，這會與現代科技中隨處可見的手提裝置理念產生衝突。為了獲得較低的操作電壓，金屬閘極將會取代傳統複晶矽閘極。 在本篇論文中，我們改善金屬矽化物─高介電常數介電質─半導體場效應電晶體的電性。在實驗中我們獲得了好的特性，P(N)型電晶體等效功函數4.95eV(4.25eV)，以及1.6nm的EOT。此外也量測到低的臨限電壓及好的遷移率。因閘極/高介電常數介面多一層Si，而使穩定性提高到1000℃。雖然仍有費米能階窄化的效應，但整個製程能在現有的技術上使用。

As the very large scale integration (VLSI) technology continues to be scaled down, the thickness of gate dielectric has to be decreased for maintaining the capacitance value and drive levels. The gate leakage current increases with decreasing thickness, and the phenomenon is counter to the mobile device in the technology node. In order to obtain small threshold voltages, we would replace poly-Si gate by metal gate. In this thesis, we improve the electrical characters of FUSI Gate-High gate dielectric-semiconductor MOSFET. We obtain good performance of proper effective work function of 4.95eV (4.25eV) for p- and n- MOSFET respectively, and about 1.6nm EOT. On the other hand, small threshold voltage and good mobility have also been measured. The thermal stability is up to 1000℃ due to the inserted Si. Unfortunately, the Fermi-Level pinning effect still occurs. However, the whole process can be used in the factory.