使用完全矽化閘極-高介電常數介電質之低臨界電壓金氧半電晶體

Abstract

為了降低傳統使用二氧化矽介電質的電晶體的漏電流，45 nm節點的互補式金氧半電晶體技術必須要使用金屬閘極/高介電常數介電質。金屬閘極理想的有效功函數，對n型金氧半電晶體來說需接近矽的導帶。然而，金屬閘極/高介電常數介電質結構仍有許多重大挑戰，其中之一為費米能階釘扎所造成的高臨界電壓。為了降低臨界電壓，其中一個方法就是使用完全矽化閘極。 在本論文中，我們做出使用完全矽化的矽化鉿閘極/氮氧鑭鉿介電質的金氧半電晶體。從量測結果中，我們得到了0.18 V的低臨界電壓、215 cm2/V-s峰值電子遷移率以及1.2 nm的等效氧化層厚度，而且其漏電流比起相同等效氧化層厚度下的二氧化矽還小了約五個數量級。此外，閘極優先的製程和熱穩定性也使得矽化鉿閘極/氮氧鑭鉿介電質電晶體與現行超大型積體電路的製程相容。

Metal-gate/high-κ is required for 45 node CMOS technology to reduce the intolerable leakage current of the conventional SiO2-based CMOSFETs. The desirable effective work function of metal gate should be close to conduction band edge of Si (~4 eV) for nMOSFETs. However, one of the key challenges for metal-gate/high-κ is the large threshold voltage due to Fermi-level pinning effect. In order to reduce the threshold voltage, it is one of the solutions to use the fully silicided gate. In this thesis, we have fabricated n-MOSFETs using fully sicilided (FUSI) HfSix gate and Hf0.7La0.3ON gate dielectrics. From the measurement, a low threshold voltage of 0.18 V and a peak electron mobility of 215 cm2/V-s is obtained at 1.2 nm equivalent oxide thickness (EOT). Also, the leakage current is about 5 orders of magnitude lower than that of SiO2 at the same EOT. In addition, the gate-first process and thermal stability of HfSix/Hf0.7La0.3ON nMOSFETs make them compatible with current VLSI fabrication process.