在二氧化鉿為基底之高介電係數閘極介電層中的載子捕捉與逃逸的電性行為

Abstract

隨著CMOS技術急速的微縮到奈米技術點，傳統以二氧化矽或氮氧化矽為閘極介電層將達到物理與電性的極限。主要的問題是量子效應引發的直接穿隧電流，導致無法接受的大量載子穿隧超薄的氧化層。高介電係數的材料當閘極介電層，它可以提供較厚的物理厚度並且得到想要的等效電性氧化層厚度，而二氧化鉿為基底的高介電係數閘極介電層已經被認為最有希望的替補者。不過，以二氧化鉿為基底的高介電係數閘極介電層具有相當嚴重的可靠度問題—臨界電壓的不穩定性，起因於高介電層早已存在的主體缺陷中的載子捕捉與逃逸現象。另一方面，我們也可以利用一些方法來減緩元件的微縮，而遷移率的增加最有用的方法之一。遷移率增加的技術提供了有效且必要的方法，讓操作電壓和功率的輸出降低，而不會失去電路的表現。 首先，高拉應力的接觸蝕刻停止層(contact etch stop layer (CESL))，對N型金氧半場效電晶體可以很明顯的增加電子的遷移率和打開的電流，而且它是最熱門的遷移率增加技術之一。所以我們會探討，拉應力效應在N型金氧半場效電晶體的基本的電性特性和載子捕捉的情形。再來，利用適合(fit)臨界電壓的偏移對施加應力(stress)/恢復(recovery)時間的數據，我們可以研究，在N和P型金氧半場效電晶體，載子捕捉和逃逸的物理機制。最後，我們要討論，氟的效應在P型金氧半場效電晶體的基本的電性特性和負偏壓高溫度不穩定性(negative bias temperature instability，NBTI) 。此外，我們利用脈波I-V的量測方法，來研究快速載子捕捉的情形。

As COMS devices are scaled aggressively into nanometer regime, the conventional SiO2 or SiON gate dielectrics are approaching their physical and electrical limits. The major issue is the intolerably huge leakage current caused by the direct tunneling of carriers through the ultrathin oxide. High permittivity materials as gate dielectrics have been proposed to offer thicker dielectric physical thickness with the desired equivalent oxide thickness in electrical properties and Hf-base high-k gate dielectrics have been recognized as the most promising candidates. However, the Hf-based high-k gate dielectrics are known to suffer from the reliability concern of threshold voltage instability due to the charge trapping and de-trapping in the pre-existing bulk traps in Hf-based high-k gate dielectrics. On the other hand, in order to retard the downscaling of Si based CMOS device, mobility enhancement is one of the most useful methods. Mobility enhancement techniques represent an effective and essential way to reduce Vdd and resulting power consumption without losing circuit performance. First, one of the most popular mobility enhancement technologies is using high tensile-stress contact etch stop layer (CESL), which can obviously improve electron mobility and ION for nMOSFETs. The basic electrical properties and the charge trapping condition of strain effect are investigated in nMOSFETs. Next, the physical mechanisms of charge trapping and de-trapping can be investigated by fitting the data of the threshold voltage shifts versus stress/recovery time in nMOSFETs and pMOSFETs. Final, the basic electrical properties and the negative bias temperature instability of fluorine effect are investigated in pMOSFETs. Moreover, the fast charge trapping is investigated by pulsed I-V measurement.