高介電係數閘極介電層在金氧半電晶體中之電特性及其可靠度研究

Abstract

隨著互補式金氧半電晶體(CMOSFETs)元件尺寸跟隨著摩爾定律(Moore’s law)持續微縮，傳統的二氧化矽(SiO2)閘極介電層(Gate Dielectrics)將遭遇極大的直接穿遂漏電流(Direct Tunneling Leakage Current)導致元件特性失效及可靠度衰退。因此，高介電係數介電層(High-□ Dielectrics)成為取代二氧化矽作為下一新世代閘極介電層最有潛力的候選。然而使用高介電係數介電層也將伴隨而至數個嚴重困難，包含了材料上的熱穩定性(Thermal Stability)、費米能階鎖定效應(Fermi-Level Pinning Effect)、通道內載子移動率的衰減(Mobility Degradation)、以及電荷被高介電係數介電層內之缺陷捕捉/散逸之現象(Charge Trapping/De-trapping)……等等。由於介電質的熱穩定性、費米能階鎖定效應、以及通道內載子移動率的衰減已分別可以藉由使用其它元素的摻雜、金屬閘極的應用、以及利用應力效應來改善其影響，而電荷在高介電係數介電層內被其缺陷捕捉/散逸之現象至今仍為尚在解決之急迫困難。 由於本論文主要是探討高介電係數介電質的電特性及其可靠度研究，針對高介電係數介電質所遭遇的問題，我們不僅在製程上尋求可以改善的適當方法，也透過量測上有系統的分析來瞭解電荷的捕捉/散逸效應其相關的現象及其物理機制。本論文一開始的首章，我們將說明半導體製程上為何需要應用高介電係數介電層，以及在長年相關研究之中所發現的幾個主要關鍵問題。第二章，我們將利用製程技術針對高介電係數介電層的幾個問題來加以改善元件特性。包括：(a)在與矽基板之界面特性研究中—我們提出利用臭氧水成長超薄氧化層(Ozone Oxide)的方法來當作在高介電係數介電質以及矽基板之間的中間介電層，有效製作出具有能改善界面特性、抵抗大量的直接穿遂漏電、以及有效減少電荷捕捉/散逸效應，並提升元件可靠度之基底介電層(Base Oxide)。(b) 在針對高介電係數介電質本體內眾多的本質缺陷—我們提出利用氟離子植入法(Fluorine Incorporation)有效地修補界面其本體內缺陷，降低電荷捕捉/散逸效應，並提升元件之電特性及其可靠度。(c)在應用高介電係數介電質之後所造成的載子移動率衰減—我們提出利用舒展性應力(Tensile Strain)在n型金氧半電晶體(nMOSFETs)上進行改善，有效的使元件的驅動電流提升，並分析出應力效應的使用對元件電特性及其可靠度之影響。此外，我們也從實驗中驗證電荷的捕捉效應將主導n通道及p通道之高介電係數介電層元件的可靠度特性。 在第三章中，為了瞭解在高介電係數介電層元件中的電荷捕捉效應(Charge Trapping Effect)，我們仔細的研究它的物理機制及其對元件可靠度之影響。我們對n型金氧半電晶體(nMOSFETs)，在正電壓及嚴苛溫度條件下，分析元件可靠度之不穩定性變化 (Positive Bias Temperature Instability, PBTI)。我們分析出在高介電係數介電層中，電子被其本體缺陷的捕捉效應有著速度上及數量上的差別。在量測上反應比較快的第一群組(0 ~ 1.78 sec)中所發生的捕捉效應我們定義為「快速捕捉」(Fast Trapping)，而相對後來的第二群組(1.78 ~ 100 sec)中所看到的捕捉效應我們稱做「慢速捕捉」(Slow Trapping)。我們發現在100秒以內的DC量測中，快速捕捉不論在數量上或者對元件可靠度的影響都佔了一個非常大的主導性。此外，我們發現在Fowler Nordheim穿遂現象的發生前後，電子由直接穿遂過基底氧化層，進入高介電係數介電層而被其內的淺缺陷捕捉，轉變成電子先穿遂到高介電係數介電層的導電帶，再被高介電係數介電層內的缺陷所捕捉。並且整個電荷捕捉現象將完全由快速捕捉效應所主導。而經由能階的計算，我們也發現這些在高介電係數介電層中反映出快速捕捉的淺缺陷，主要是為HfO2中的Vo2+, Vo-, Vo2- 以及晶體邊界缺陷 (grain boundary defects) 在第四章中，我們利用與第三章相同的元件及分析方式，在回復電壓的條件下對電荷的散逸效應(Charge De-trapping Effect)仔細地進行研究及討論。在電荷的散逸效應中，同樣有著速度上及數量上的差別。反應比較快的散逸效應我們定義為「快速散逸」，而相對較慢的我們稱做「慢速散逸」。同樣的快速散逸效應在整個電荷回復行為中有著相當大的主導性。此外，我們發現整個電荷散逸效應的能力，主要是由高介電係數介電層中可允許穿遂回矽基板的能階所決定。 在第五章中，而針對一般DC量測無法精準萃取的快速暫態電荷捕捉/散逸效應，我們也導入具有極短量測時間並可解析數奈秒(ns)下電荷行為之優勢的脈衝式量測(Pulse IV Measurement)，來正確完整的分析在高介電係數介電層中的電荷捕捉/散逸效應。對幾個重要的物理參數，諸如：逼迫電壓，逼迫時間，回復電壓，以及較嚴峻的操作溫度。我們分別有系統的進行完整的相關研究，並探討其背後的物理意義。此外，我們也利用脈衝式量測模擬了高介電係數介電層元件在AC電壓形式操作下的情況。我們除了發現電荷的捕捉/散逸效應在AC電壓形式的操作下，對元件的電特性及可靠度仍有顯著的影響。 因此在第六章中，針對元件在連續的電壓操作下，我們仔細的討論電荷捕捉/散逸效應對高介電係數介電層元件的電特性及其可靠度之影響。我們發現在回復電壓不足的情況下，被捕捉在高介電係數介電層本體內部的電荷將會持續留存，並累積在下一次電荷捕捉效應之中。而透過一個足夠回復電壓的條件來分析，我們可以知道整個電荷捕捉/散逸效應是具有回復性。繼而證實在小電壓逼迫的條件下，並無造成高介電係數介電層中任何額外的缺陷產生，只是重複電荷捕捉/散逸的行為。因此，我們所看到劣化的元件動態可靠度之不穩定性是由於在高介電係數介電層本體中，未能散逸而出的電荷在重複的電荷捕捉/散逸的效應下進行了存留電荷的累積，而非新的缺陷在小電壓電性逼迫中產生。如此，我們也映證了電荷的捕捉/散逸現象將對元件連續操作造成顯著的影響。 在第七章中，我們對p型金氧半電晶體(pMOSFETs)，在負電壓及嚴苛溫度條件下，分析元件可靠度之不穩定性變化(Negative Bias Temperature Instability)。在NBTI的研究中，我們除了分析電洞在高介電係數介電層中的被捕捉特性，也藉由一個奇異的NBTI現象(Anomalous NBTI Behavior)，額外發現電子在NBTI的可靠度衰退中也扮演一個不可忽視的角色。因此，當我們在利用NBTI可靠度考量元件的生命週期之時，我們將需要慎重考量電子在p型高介電係數閘極電晶體中的捕捉現象，並用此修正整個元件生命週期的預測。 於高介電係數介電層之可靠度研究中，在考量了電荷的快速暫態行為所帶來的影響，我們完整地建立了一個具有通用性的物理模型，並可合理的解釋在高介電係數介電層中之電荷捕捉/散逸效應的物理機制。最後，我們也根據這些年來研究高介電係數介電層的經驗，針對高介電係數介電層在未來的研究方向提出一些看法。

As the CMOS technology continues to scale down following the Moore’s law, the shrinkage of gate dielectric thickness will suffer the intolerable direct tunneling gate leakage current which leads to degrade the device performance and reliability. High dielectric permittivity gate dielectrics (high-□ gate dielectrics) have been proposed to be the potential candidates to solve these critical issues since their thicker films can be utilized to reduce the large direct tunneling leakage current while maintaining EOT value and the device performances. However, several critical problems such as thermal stability, Fermi-level pinning effect, channel mobility degradation, and charge trapping/de-trapping effects have accompanied with the progress of high-□ gate dielectrics. The thermal stability, Fermi-level pinning effect, channel mobility degradation have been improved through the multi-element incorporation, metal gate process, and application of strain effect, respectively. However, the charge trapping/de-trapping effects are still the major difficulties which are waiting for the effective solutions in the progress of the high-□ gate dielectrics. For completing the high-□ researches, the aims of this dissertation will not only effectively enhance the related issues of high-□□ devices through appropriately fabrication technologies, but also systematically investigate the dynamics of charge trapping/de-trapping effects and the related physical mechanisms through a variety of electrical characterizations. At beginning, in chapter 1, we will explain the necessary of high-□ gate dielectrics applied on semiconductor fabrication, and further point out several critical issues discovered during related investigations in recent years. In the early stages of this dissertation, we studied the enhancements of device performance through the fabrication technologies. The ozone oxidation has been verified to effectively improve the interfacial properties between high-□□ gate dielectrics and Si-substrate with fine interface properties, low direct tunneling leakage current, and less charge trapping effect. The fluorine incorporation has been confirmed to apparently reduce the high-□ bulk traps and enhance the device performance and reliability. The tensile strain effect has been demonstrated to successfully enhance the n-channel electron mobility. Besides, the charge trapping effect has been verified to dominate the reliability degradation in both nMOSFETs and pMOSFETs with the high-□ gate stack. For understanding the impacts of charge trapping/de-trapping on the device reliability, the related investigations have been conducted in both nMOSFETs and pMOSFETs through the PBTI and NBTI degradations. In PBTI researches, we have observed the influences of trapping charges at the high-□ bulk trap centers on the associated reliability, and have established a physical model to properly explain the mechanism. Moreover, in NBTI studies, we have not only analyzed the related characteristics of hole trapping in the high-□ bulk, but also discover that the careful considerations of both holes and electrons in NBTI degradation are necessary. In both charge trapping/de-trapping phenomena, the experimental results have been discussed as the fast transient behavior and slow behavior in the aspects of distinct time respondences. We have found both significantly quantitative and qualitative differences between fast transient behavior and slow behavior. On one hand, the charge trapping behavior has been systematically investigated on the stages of stress voltage and stress time. On the other hand, the charge de-trapping behavior also has been carefully studied through the stress voltage and recovery voltage. From the experimental results, we have constructed a reasonable physical mechanism. In order to actually realize the charge trapping/de-trapping behaviors, the pulse IV measurement have been applied to monitor the electrical characterizations with the considerations of fast transient behaviors. All of related investigations have been conducted with the critical concerns of fast transient behaviors to further complete the physical mechanism in charge trapping/de-trapping phenomena. In addition, the charge tunneling has been demonstrated to be the predominance in the charge trapping/de-trapping phenomena through less dependence on the variety of temperatures. Further, the AC stress has also been verified to have apparent impacts on the continuing device operation. Therefore, we have built a universal model to appropriately explain the physical mechanisms of charge trapping/de-trapping effects with the important considerations of fast transient behaviors.