以離子植入矽化物技術製作在矽化鎳與矽介面間形成陡峭接面之熱穩定度相關研究

Abstract

在互補式金氧半電晶體的元件尺寸持續縮小時，閘極漏電流和接觸電阻等問題便顯得格外的重要。隨著高介電材料的研究與應用，低溫的半導體製程也逐漸受到重視。在我們的實驗中，為了降低接觸電阻與接面寄生電阻，我們採用了金屬矽化物技術。而矽化鎳因為擁有低的電阻率和低的矽消耗量被我們用在做為金屬矽化物的材料。另外，我們結合了離子植入矽化物技術和固態磊晶再成長的觀念，以達成低溫形成薄陡峭接面的目的。我們的實驗是將BF2+與P+植入矽化鎳，再經由快速升溫退火裝置製成陡峭接面。在這篇論文中，主要探討的是在矽化鎳與矽介面間形成陡峭接面的熱穩定度相關研究。我們利用額外的退火步驟，研究當陡峭接面形成後，再經類似溫度的熱製程，對電性有何影響。我們得到在實驗設計中，以約550℃的溫度退火，是較良好的製程條件；在經額外的熱製程後，有雜質析出現象與雜質堆集效應的存在。最後，我們也發現在高於550℃的退火，矽的自我結晶形成的缺陷會讓漏電流上升，而低於550℃則是由於已活化雜質的析出而導致漏電流上升。

When the pattern size of device continuously narrows for CMOS transistor, the issues of gate leakage and contact resistance are more important. Depending on the high-k dielectric material research, low temperature process is a trend. In our experiment, to reduce the contact resistance, we adopt the metal silicide technology. Nickel material is used be our silicide film due to its low electrical resistance and low silicon consumption. Additionally, we combine the concept the implant into silicide (IIS) technique and solid phase epitaxial regrowth (SPER) to fabricate the shallow junction at low temperature. As a result, NiSi-silicided shallow junctions are fabricated by BF2+/P+ implantation into a thin NiSi silicide layer, follow by rapid thermal annealing (RTA). In this thesis, the thermal stability of NiSi-silicided shallow junctions is investigated with respect to their electrical characteristics by I-V measurement and C-V measurement. We introduced the additional thermal process after the junction formation. the annealing temperature around 550℃ is the widest process for junction formation in our experiment. And the dopant de-activation phenomenon and dopant segregation effect are discovered. Finally, when additional annealing temperature above 550℃, the defect formed in Si itself dominated the leakage current of samples, and below 550℃, the dopant de-activation dominated it.