奈米低壓差穩壓器的擺放

Abstract

在莫爾定律的驅動下，電路的複雜度在這幾十年來有指數性的成長。數位電路的設計因為有了許多自動化的工具而有爆炸性的成長，相反地，類比電路需要大量的修正以及較長的設計時程以便因應製程更動。一個穩定的類比電路需要多次的修正流程讓系統規格不會因為製程、供給電壓以及操作溫度而受到相當大的影響。隨著製程進入奈米層級，電路便很容易受到短通道效應而造成校能低落。

為了讓類比電路能和數位電路一樣有更簡易的設計流程，我們提出了一個自動化的設計以及佈局流程並且以低壓差穩壓器為例子。我們的演算法考慮元件匹配性，面積最小化，以及繞線可行性，並且以工業設計當作實驗輸入，驗證我們的擺放器可以應用在實際工業用途。

As are motivated by Moores law, the circuit complexities for VLSI system are growing exponentially in the past decades. Digital designs are benefited from many powerful automatic design tools. However, the analog counterpart still demands huge engineering efforts and lengthy design period for technology migration. For a robust analog design may require several iterations to fulfill all the system specifications under process, voltage, and temperature variations, this scenario may become worse since many short channel effects are more pronounced as the devices step into the nanometer arena.

In order to bridge the gap between analog and digital VLSI design capability, this work presents a framework for analog IP automatic design and layout synthesis. Employing low drop out regulator as a vehicle, the placer can generate a compact and regular layout a given circuit topology. In contrast to solving many overlooked circuit equations, the proposed complier is based on analog expert system concept and combines with simulated annealing. It can achieve the target goals for the first time right without time-consuming iterations. The layout synthesis part also automatically takes many design constraints for device matching and area optimization into considerations. To verify the performance of the placer, industrial cases are used to verify the correctness and quality of the resulting layout. The experimental results showed that our methodology can successfully apply to practical cases with rather compact and regular placement.