適用於展頻時脈之數位相位調整的時脈資料回復電路

Abstract

各式的高效能低成本串列傳輸技術廣泛應用於各種現代電子產品中，而時脈 資料回復電路則是高速串列傳輸系統的接收端中最關鍵的部分。現代時脈資料回 復電路設計的趨勢包括：隨著資料頻寬的提升與成本的下降，多通道的串列傳輸 已成為主流。而數位設計的時脈資料回復電路往往比類比電路設計更適合於此類 應用且不受製程/電壓/溫度變化的影響。另外，為了對抗電磁波干擾的問題，展 頻技術也被運用在資料傳輸內，因此時脈資料電路需要具備從展頻時脈中回復正 確資料的能力。 在高速時脈資料回復電路中，二元相位偵測器是主流的趨勢。但是二元相位 偵測的非線性行為卻會為相位追蹤迴路帶來諸多不利影響，如：增益隨抖動量改 變、穩態下振盪等。因此我們提出「多重交替式轉態取樣技術」及「增益補償」， 能有效的使二元相位偵測器的增益線性化，從而達到穩定的相位追蹤。 展頻技術是對時脈信號的頻率做微量的調變，使其在頻譜上分散在較寬的頻 帶範圍，因此可降低時脈造成的能量峰值。提出的展頻時脈產生器以鎖相迴路為 基本架構，並使用和差調變器及相位旋轉方式完成之。我們所提出的展頻時脈產 生器主要應用於第三代Serial ATA 中，向下展頻5000ppm 同時採用三角波調變 且調變頻率為30KHz。本論文的主題之一即是討論不同階數之和差調變器的影 響。由我們理論的結果顯示，只要相位內插器解析度夠細，不同階數的調變器所 造成的抖動差異是小到足以被忽略的。 實作晶片使用聯電標準臨界電壓90 奈米互補式金氧半導體製程來製造，佈 局後之模擬的資料頻率為5.5Gbps 到6.5Gbps，回復時脈的峰對峰抖動值為 17.52ps。展頻時脈最大週期對週期時脈抖動為1.13ps 並操作在1.4GHz 時消耗 7.57 毫瓦。能量峰值所能降低的最大數量為20.6dB。

Recently, many high-speed and low cost serial link transmission technologies are developed and are widely used in modern electronic products. The clock and data recovery module is the most important component in the receiver end of high speed serial link systems. Modern trend of CDR circuit design includes: First, as the increase of transmission bandwidth and the decrease of fabrication cost, multi-channel transmission system has become the mainstream. Second, digitally implemented CDRs are often more favorable than analog ones for the broad applications and robustness against PVT (process, voltage, temperature) variations. Finally, in order to reduce EMI (electro-magnetic interference) problem, spread spectrum clock technology is used in data transmission. Therefore, it is necessary for CDR to recover correct data from spread spectrum clock transmission. In the high speed CDR, binary phase detection is the mainstream. However the non-linear characteristic of binary phase detection introduces unwanted effects like PD gain varies with jitter amplitude, and oscillatory steady state of phase tracking. Therefore we propose a Multiple-Alternating Edge Sampling (M-AES) scheme and Gain Compensation to linearize the PD gain and achieve a stable phase detection. Spread spectrum technique slightly modulates the frequency of clock signal and spreads it over a wider bandwidth. This would lead to a reduction of the peak level of the clock energy. A spread spectrum technique using PLL with a sigma delta modulator and phase rotation algorithm is proposed. Our spread spectrum clock generator (SSCG) for Serial ATA III Specification is down spread 5000ppm with a triangular modulation profile and the modulation frequency is 30 KHz. One objective of this thesis is to analyze the effect of different order of ΣΔ modulation. Our theoretical results have shown that, once the phase resolution of the interpolator is high enough, the difference of the jitter from different order of modulators is so insignificant that can be neglected. The test chip is fabricated in UMC 90nm CMOS regular-Vt process. The post-layout simulated data rate from 5.5Gbps to 6.5Gbps, the peak-to-peak jitter is 17.52ps. The spread clocking has a peak-to-peak cycle-to-cycle jitter of 1.13ps and consumes 7.57mW at 1.4GHz. The EMI reduction in this circuit is about 20.6dB. The analog circuit power consumption is 55mW under 1.0V supply voltage.