區別製程邊界來提高記憶體編譯器產生出來的靜態隨機記憶體良率

Abstract

當製程持續的縮小至奈米等級時，因為晶粒與晶粒間的變異，將使得良率降低的情況越來越嚴重，而使用適當的基版偏壓技術可以有效的減小這個問題。然而要運用這一項技術我們必須先知道一個晶粒是屬於高臨界電壓或是低臨界電壓(也稱之為製程邊界)。但是很不幸地，當PMOS與NMOS的變異是沒有關聯時我們將很難偵測出他們的製程邊界。在這篇論文中，我們針對延遲監視器與漏電流監視器這兩種電路做了一些改善，使得當PMOS與NMOS變異為不相關時也能分別偵測出他們的製程邊界。由實驗結果我們可以看出我們的電路可以清楚的區別製程邊界，因此可以順利的採用正確的基板電壓來提升良率。

As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or low threshold voltage (also called process corner) in order to use this technique. Unfortunately, it is hard to detect the process corner when PMOS and NMOS variations are uncorrelated. In this thesis, we propose some improved circuits of delay monitor and leakage monitor for both PMOS and NMOS having inter-die variations, and are uncorrelated. The experimental results show that our circuits can clearly distinguish each process corner of PMOS and NMOS, thus improve the yield obviously by adopting correct body bias.