使用金屬平衡演算法來降低時鐘樹架構受製程變數的影響

Abstract

隨著製程技術的進步，我們越來越難達到零偏斜或接近零偏斜的時鐘 分配，即使經過一些常見的演算法來合成零偏斜的時鐘。在本篇論文 中，我們提出了一個方法，透過平衡各金屬層的繞線長，來增強時鐘 架構對製程變數的抗性。由實驗結果可以得知，我們的方法使用在無 插入緩衝器和插入緩衝器兩種時鐘樹合成，能比DME演算法更有效的 降低因製程變數所產生的偏斜。

With advanced manufacturing technology, it is getting difficult to have zero or almost zero-skew clock distribution, even the clock is synthesized to be zero-skew from conventional algorithms. In thiswork, we proposed a practical problem in clock construction with process variation awareness, which is to achieve the balance of the wirelength in preferred direction metal routing. Experimental results show that our approach (unbuffered and buffered clock tree syntheses) performs better than conventional DME algorithms in reducing the skew of the clock.