內建基底雜訊量測電路

Abstract

本論文提出一個新的基底雜訊量測電路，配合上自我偵測PVT (製程、電壓、溫度)的電路，作動態頻率調整，使得 (SoC) 系統晶片能夠工作其最佳的工作狀態。在量測基底雜訊方面，不同於之前量測雜訊電壓的方法，取而代之的是以雜訊對電路所造成的時間抖動量，判斷雜訊對電路影響的大小。我們以一個壓控震盪器將電壓偶合進基底產生基底雜訊，經由反向器串鏈吸收基底雜訊，將雜訊轉換成時間抖動量(Jitter)。並用一個時間抖動偵測器，偵測時間抖動的大小。 此電路另有一個以PRBS、數位電路、MISR組成的驗證電路，並且設計一個與數位電路相同組合邏輯深度的迴圈震盪器，量測其震盪頻率，以偵測目前工作的PVT狀態。如此，我們則能夠根據PVT與雜訊的偵測結果，藉由動態頻率調整，得到最佳的工作狀態。此晶片使用台積電 0.18 m RF CMOS 製程來實現。在1.8V的電源供應下，總功率消耗為26mW，其中量測電路所佔的功率消耗為14.7mW。

This thesis proposes a circuit to measure the substrate noise. This circuit cooperates with a PVT (Process, Voltage, Temperature), and a noise monitoring circuit to make a SoC (System on Chip) operates at its optimal operating point. For the substrate noise measurement, instead of measuring the noise amplitude, we measure the timing jitter of the circuit caused by the substrate noise. It determines the degree that the circuit is affected by the noise. The noise is coupled into the substrate from a voltage-control oscillator and absorbed by an inverter chain. The noise is transformed into timing jitter and detected by circuit This circuit also includes a verification circuit, made up of a PRBS, a digital circuit, and a MISR. A ring oscillator is designed to have the same combinational depth as that of the digital circuit to detect the current PVT status. According to the results of the noise measurement and PVT corner, we use dynamic frequency scaling to decide the optimal working condition for the circuit. This chip is implemented in TSMC 0.18um RF CMOS process. In a 1.8V power supply, the jitter measurement circuit consumes 14.7mV, and the total power consumption is 26mW.