使用三倍頻器產生本地震盪訊號的升頻混波器

Abstract

本論文主要在於設計一個能提供足夠寬的中頻頻寬的升頻混波器，以應用在60-GHz頻段來達到高資料量傳輸的目的。此升頻混波器使用一個三倍頻器來提供其本地震盪訊號。此外，又特別針對三倍頻器提出了新的架構，經由仔細的分析，此三倍頻器能更有效地產生三倍頻的訊號。 在本論文中共實現兩顆晶片，第一顆晶片為具有寬的中頻頻寬的升頻混波器，使用TSMC 0.13-μm CMOS製程。量測結果顯示其在2.7 mW的功率耗損下，有-5.6 dB的轉換增益，並提供了3.5 GHz的中頻頻寬，使其適用於高速資料傳輸。 第二顆晶片為所提出的次諧波電流注入式三倍頻器，使用TSMC 0.18-μm CMOS製程。模擬結果顯示其在僅2.6 mW的動態功率耗損下，有-5.7 dB的轉換增益。此外，此三倍頻器能有效地鎖定I/Q訊號的不均衡，使其在通訊系統整合上具有相當的潛力。

This thesis aims at the design of an up-conversion mixer with wide intermediate frequency (IF) bandwidth for providing high data-rate transmission at 60-GHz band. A frequency tripler is used to provide local oscillator signal for the up-conversion mixer. In addition, we propose a novel structure for frequency tripler. Through detailed analysis, this proposed frequency tripler can generate the third-order harmonic efficiently. Two chips are realized in this thesis. In the first chip, an up-conversion mixer with wide IF bandwidth is fabricated using TSMC 0.13-μm CMOS technology. Experimental results show -5.6dB conversion gain and 3.5-GHz IF bandwidth under 2.7mW power consumption, which is feasible for high-speed data transmission. In the second chip, the proposed harmonic current injection frequency tripler is fabricated using TSMC 0.13-μm CMOS technology. Simulation results show -5.7 dB conversion gain under only 2.6 mW dynamic power consumption. In addition, this frequency tripler can lock the input I/Q imbalance, which makes its great potential in the integration of communication systems.