以電流再利用之CMOS射頻前端關鍵元件設計

Abstract

本論文分為具帶拒濾波之低雜訊放大器和具內建震盪器之低功率混頻器兩個部分。利用標準TSMC 0.18 um RF CMOS 製程完成本論文中所設計的電路。 第一部分描述設計一個低功率之帶拒濾波低雜訊放大器。其量測結果之power gain在3~10GHz內大於9.5dB，NFmin為2.6dB，S11<-5.4dB，不包含緩衝級之功率消耗為6.8mW，接著使用主動式電感實現之微小化的帶拒濾波器，使得整體電路之core area只有0.0016 mm2。其量測之power gain為8~12dB、S11<-11dB、在2.5GHz和5.2GHz頻段附近抑制干擾訊號的效果分別為19dB及38dB，功率消耗為10.3mW，模擬之NFmin為2dB、P1dB為-14.2dB。 第二部分描述震盪器與混頻器之結合與設計。使用電流再利用的方式達到低功率的效果，並進一歩將平衡非平衡轉換器整合在電路中，它包含了一個混頻器和震盪器及一個balun。此整體電路可達功率增益為15dB，S11<-12dB，功率消耗為6mW。

The thesis consists of three parts: low noise amplifier, LNA with notch filters and low-power oscillator mixer. These propose circuits are fabricated using a standard TSMC 0.18 um RF CMOS process technology. The first part of the thesis is the low power design of low noise amplifier with notch filters. The measurement result of LNA shows the power gain is more than 9.5dB in 3~10GHz, return loss is under -5.4dB, NFmin is 2.6dB, and power consumption exclude buffer is 6.8 mW. Then, we use the design of the miniaturized notch filters realized by active inductor, applied in the integration of LNA. The core area of LNA and notch filters is only 0.0016 mm2. The measurement result of LNA with notch filter shows the power gain is 8~12dB, return loss is under -7.5dB. The suppressed performance of notch filters in 2.5GHz and 5.2 GHz are 19dB and 38dB. The power consumption is 10.3 mW. The simulation results of minimum noise figure and P1dB are 2dB and -14.2dB. The last part describes the combination of VCO and mixer. The circuit uses current-reuse to reach low power consumption, and furthermore a balun is integrated in this design. The total schematic contains mixer, VCO, and on-chip balun. The chip area is 1mmx1.5mm. The simulation results show the conversion gain are 15dB, return loss is under -12dB, P1dB is -16dB. The phase noise is -105 dBc/MHz. The total power consumption is 6mW.