全積體化低電壓低功率之CMOS電壓控制振盪器設計

Abstract

摘要 在目前無線通訊技術系統快速發展之下，研發低成本、高效能、低功耗之無線射頻積體電路日益迫切。過去，因其在高頻的高效能之原因，射頻前端電路多採用矽鍺（Silicon Germanium；SiGe）BiCMOS為主流製程，然而隨著標準CMOS製程技術日趨成熟，目前採用此製程之比重已逐年提高，預計在2009年時，將約有40％的射頻收發機電路改採CMOS製程技術。由於CMOS製程早已導入基頻晶片多年，若是射頻電路也採用相同製程，將有助於晶片之整合，在成本降低、整合度提高之驅動下，將掀起無線通訊市場之另一波成長；另外，在手持行動裝置中，因射頻前端電路為最耗電之其中一部分，使得電源供應無法長效使用，尤其在輕薄短小之目標下，功耗問題往往限制了其應用發展，因此，研發更具成本效益的電路同時達到低功耗的目的，將是迫於解決的問題。本篇論文的研究焦點著重於降低電壓控制振盪器其供應電壓及功率消耗之設計，同時在低功耗程度維持一定的相位雜訊水準。利用傳統交叉對耦式的架構，以最少疊接級數中增加一對NMOS平行於電感電容共振腔，其提供的寄生電容Cgs、Cgd與交叉對耦電晶體產生額外負電導，此負電導與等效電容可有效降低相位雜訊，另外，我們在此NMOS之基體端加上偏壓，此一步驟將與可變電容器產生共軛壓差，進而降低共模雜訊，同時，因此NMOS以閘極端連接共振腔，故不增加額外壓降及直流功耗，使在最少疊接級數中能將電壓完全供應給後級的交叉對耦電晶體，達到低電壓、低功耗目的。由量測結果(TSMC 0.18-μm 1P6M CMOS 製程)，在距離中心頻率1-MHz相位雜訊為-112.24dBc/Hz。此設計的供應電壓為0.51V，消耗功率為1 mW，其工作頻率為3.3GHz，晶片面積為0.61(μm)×0.76(μm)。

Abstract As the advancement of wireless communication system growing rapidly. Development of radio frequency (RF) integrated circuits in low cost, high performance and low power consumption is more and more imminently. In the past, the RF front-end circuits are made by SiGe BiCMOS process technologies due to its high performance in high frequency. However, with the standard CMOS process technology getting proficient, RF front-end circuits made by CMOS process are more and more popular. As far as the actual applications are concerned, the RFICs are power-hungry devices which cause the battery life time could not be extended effectively. The problem of power consumption further restricts the applications in wireless electronic devices, especially in the demands of light, thin, short and small devices. Therefore, development of RFIC more efficient in cost and low power consumption is an emergent issue to solve. This thesis focuses on the design of low supply voltage and low power consumption and maintains comparable level of phase noise simultaneously. Using a conventional NMOS cross-coupled LC-VCO architecture which has the least stages stacked in vertical could be reduced the supply voltage. By adding a proposed NMOS pair which paralleled the LC-tank, the parasitic capacitances Cgs, Cgd of the proposed NMOS pair generate an additional negative conductance, as a result, the phase noise can be degrade effectively in low power, low supply voltage operation level. Besides, the bodies of proposed NMOS pair are biased, which generate an opposite voltage drop as compared with varactors. As a result, the common mode noise is reduced. Eventually, the goals of low power consumption and low supply voltage can be achieve due to most of the supply voltage feed the cross-couple NMOS and the added NMOS pair take no voltage drop. The proposed low voltage, low power LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process. With only 0.51 V bias, the power consumption of the proposed LC-VCO is 1 mW. The phase noise is -112.24 dBc/Hz from 1 MHz offset frequency at 3.3GHz and the chip size of 0.61 (μm) × 0.76 (μm).